1. Field of the Invention
An aspect of the present invention relates to a semiconductor device including transistors and ferroelectric capacitors.
2. Description of the Related Art
As one nonvolatile semiconductor memory, attention is focused on ferroelectric random access memory (FeRAM) with memory cells each made up of a transistor and a ferroelectric capacitor, as disclosed in JP-A-2005-268472. This kind of ferroelectric random access memory adopts a COP (capacitor on plug) structure in which an electrode of the ferroelectric capacitor and a source/drain of the transistor are electrically connected by using of a contact plug from the viewpoint of area penalty.
Characteristic degradation of the ferroelectric capacitor easily occurs due to the reduction by the hydrogen. Thus, JP-A-2005-268472 further discloses a structure wherein a hydrogen barrier film for covering and protecting a ferroelectric capacitor is formed.
In ferroelectric random access memory having such ferroelectric capacitors, for example, an alumina film is used as a hydrogen barrier film and is formed in a film thickness of several ten nm to several hundred nm. A lower layer insulating film (interlayer insulting film) such as a silicon oxide film having a film thickness of several hundred nm is formed on a transistor and the hydrogen barrier film is formed on the lower layer insulating film. Further, an upper layer insulating film (interlayer insulting film) such as a silicon oxide film having a film thickness of several hundred nm is formed on the hydrogen barrier film. Metal wiring connected to the source or the drain of the transistor and metal wiring connected to the electrode of the ferroelectric capacitor are disposed on the upper layer insulating film. That is, metal wiring is disposed through the lower layer insulating film, the hydrogen barrier film, and the upper layer insulating film on the source and the drain of the transistor and the gate electrode.
A contact opening is formed in the upper layer insulating film, the hydrogen barrier film and the lower layer insulating film, and the metal wiring is electrically connected to the source or the drain of the transistor and the gate electrode through the contact opening. Generally, the contact opening is hard to manufacture, and the manufacturing of the contact opening negatively affects the yield in the manufacturing process of ferroelectric random access memory. Specifically, if the contact opening is manufactured with the etching condition of reactive ion etching (RIE) matched with a silicon oxide film, the etching rate of the hydrogen barrier film becomes extremely low as compared with the etching rate of the silicon oxide film. In such a manufacturing process condition, the etched cross-sectional shape of the hydrogen barrier film becomes like taper and the opening dimension of the bottom of the contact opening is extremely scaled down.
JP-A-2005-268472 also discloses a method for forming a tungsten (W) plug on the source/drain of a transistor, to which the ferroelectric capacitor is not connected, in a lower layer insulating film, and for forming a hydrogen barrier film just above the W plug. According to this method, since the tungsten (W) plug is formed in the lower layer insulating film, the lower layer insulating film having a thick film thickness does not exist between the W plug and the hydrogen barrier film. That is, the taper shape of the hydrogen barrier film whose RIE working is difficult to perform may be controlled in the film thickness range of several ten nm to several hundred nm and thus the bottom dimension of the contact opening can be increased and the cross-sectional shape of the contact opening can be controlled easily.
As finer design rules of ferroelectric random access memory proceed, for example, if the one-side size of a contact opening becomes less than 0.2 μm in the 130-nm generation of the minimum working dimension of the manufacturing process, the aspect ratio of the contact opening increases. This means that the ratio of the depth to the opening area of the contact opening increases. For example, the source/drain region of a transistor is formed of silicon (Si), and a barrier metal film is formed between the source/drain region and a W plug. The surface portion of the source/drain region is formed of, for example, a cobalt silicide (CoSi) layer. A layered film made up of a titanium (Ti) film and a titanium nitride (TiN) film deposited on the titanium (Ti) film is used as the barrier metal film. If the aspect ratio of the contact opening increases, the step coverage of the barrier metal film on the bottom and the inner wall of the contact opening decreases, and particularly the film thickness of the Ti film formed on a side wall becomes extremely thin. Consequently, coagulation of a titanium silicide (TiSi) film occurs in the contact opening by heat treatment accompanying the manufacturing process of a ferroelectric capacitor, and the action of reducing the precipitate of diffusion layer impurities onto the CoSi layer becomes insufficient. Such a phenomenon increases the resistance value in the contact opening, causing a contact failure to occur. The contact failure can be solved by increasing the film thickness of the Ti film of the barrier metal film and reducing the aspect ratio of the contact opening.
However, if the aspect ratio of the contact opening on the source/drain is reduced, the aspect ratio of the contact opening on the gate electrode is further reduced since the top of the gate is disposed above the source/drain. This means that the height of the W plug electrically connected to the gate electrode and formed in the contact opening becomes extremely low as much as the film thickness of the gate electrode. Since the hydrogen barrier film is hard to etch in the etching condition matched with the silicon oxide film as described above, a metal etching gas using a chlorine-based gas is used for RIE to etch the hydrogen barrier film. When using the metal etching gas, undesirable etching on the W plug disposed under the hydrogen barrier film is occur in the etching of the hydrogen barrier film. Here, when embedding the W plug in the contact opening according to an MOCVD method, a seam of the plug material is generated on the center portion of the contact opening, and the etching rate becomes extremely high on the seam. Therefore, in the W plug in the contact opening on the gate, the W plug is penetrated by an etching, and the etching reaches the gate electrode when the hydrogen barrier film is etched. For example, a layered film made up of a silicon polycrystalline film and a high melting point metal silicide film deposited on the silicon polycrystalline film is used as the gate electrode. If penetration of the W plug occurs, the etching proceeds to the high melting point metal silicide film of the gate electrode, and the electric connection between the gate electrode and the W plug becomes contact of the silicon polycrystalline film and the W plug and thus the resistance value not only varies, but also increases.